Terminal cells are employed in integrated semiconductor circuits to make a contact from the integrated circuit to external circuits. In particular, such contacts serve to feed supply voltages or reference voltages. In addition, control signals, data signals or any other signals can be sent to or taken from the integrated circuit via the contacts.
Fault situations can arise in the operation of the integrated circuit, for example, if overvoltages are applied to the contacts or because of electrostatic discharges. So that such overvoltages do not cause damage or destruction of the integrated circuit, protective elements through which the resulting currents can be drained are used in many cases. However, due to the design of the field-effect transistor structures in combination with the substrate of the semiconductor body of the integrated circuit parasitic bipolar structures form, through which significant currents arise in the event of a fault. In particular, currents are produced in the substrate that, under certain voltage conditions, lead to a permanent low-resistance condition in the parasitic bipolar structures. In many cases this can lead to destruction of the semiconductor body having the integrated circuit. Such a condition is also known as a latch-up effect.
To limit the consequences of a latch-up effect, it is proposed in traditional circuits to detect a current in the substrate and, if a current is detected, to disconnect the circuit from the corresponding terminals or contacts via a built-in switch. However, since in this case a fault current has already developed in the substrate, destruction of the semiconductor circuit cannot be prevented under certain circumstances, especially since a significant number of charge carriers are already moving in the substrate. Furthermore, a function of the circuit becomes limited or completely interrupted by the disconnection of the contact from the circuit.
US 2006/0223258 A1 concerns a manufacturing process for a semiconductor body having complementary metal-oxide semiconductor transistors and a bipolar transistor. A protective arrangement comprises a trigger element and a protective element having two bipolar transistors.